EPSON S1D13705
Register Quick Reference

This is to be used as a quick reference only (USB registers are not included). Please refer to the S1D13705 Hardware Functional Specification for details of each register.
This reference was generated by 13705CFG.EXE (Build 9).

REG[00h] Revision Code Register
Product Code [RO]
Rev Code [RO]
7
6
5
4
3
2
1
0
Bits 7:2Product Code [READONLY]
Bits 1:0Revision Code [READONLY]

REG[01h] Mode Register 0 Register
TFT/STN
Dual/Single
Color/Mono
FPLINE Pol
FPFRAME Pol
Mask FPSHIFT
Data Width Bits
7
6
5
4
3
2
1
0
Bit 7TFT/STN = bit7 where { 0=STN | 1=TFT/D-TFD }
Bit 6Dual/Single = bit6 where { 0=Single | 1=Dual }
Bit 5Color/Mono = bit5 where { 0=Mono | 1=Color }
Bit 4FPLINE Polarity = bit4 where { 0=Active Low | 1=Active High }
Bit 3FPFRAME Polarity = bit3 where { 0=Active Low | 1=Active High }
Bit 2Mask FPSHIFT = bit2 where { 0=Disabled | 1=Enabled }
Bits 1:0Data Width Bits

REG[02h] Mode Register 1 Register
Bits-Per-Pixel
High Perf
Input Clock Div
Disp Blank
Frame Repeat
HW Invert
SW Invert
7
6
5
4
3
2
1
0
Bits 7:6Bits-Per-Pixel (in BPP)
Bit 5High Performance = bit5 where { 0=Makes MCLK=PCLK/(8/BPP) | 1=Makes MCLK=PCLK }
Bit 4Input Clock Divide = bit4 where { 0=Makes CLK=CLKI | 1=Makes CLK=CLKI/2 }
Bit 3Display Blank = bit3 where { 0=Disabled | 1=Enabled }
Bit 2Frame Repeat (EL Support) = bit2 where { 0=Disabled | 1=Enabled }
Bit 1Hardware Video Invert = bit1 where { 0=FPDAT11 becomes GPIO4 | 1=Invert using FPDAT11 }
Bit 0Software Video Invert = bit0 where { 0=Disabled | 1=Enabled }

REG[03h] Mode Register 2 Register
n/a
n/a
n/a
n/a
LCDPWR Override
HW Power Save
SW Power Save
7
6
5
4
3
2
1
0
Bit 3LCDPWR Override = bit3 where { 0=Disabled | 1=Enabled }
Bit 2Hardware Power Save = bit2 where { 0=No Effect | 1=GPIO0 used as Power Save }
Bits 1:0Software Power Save = bits1:0 where { 0=Power Save | 1,2=RESERVED | 3=No Effect }

REG[04h] Horizontal Panel Size Register
n/a
Horz Size
7
6
5
4
3
2
1
0
Bits 6:0Horizontal Panel Size (in pixels) = ( bits6:0 + 1 ) * 8

REG[05h] Vertical Panel Size Register (LSB)
Vert Size (LSB)
7
6
5
4
3
2
1
0
Bits 7:0Vertical Panel Size (LSB)

REG[06h] Vertical Panel Size Register (MSB)
n/a
n/a
n/a
n/a
n/a
n/a
Vert Size (MSB)
7
6
5
4
3
2
1
0
Bits 1:0Vertical Panel Size (MSB)

REG[07h] FPLINE Start Position Register
n/a
n/a
n/a
FPLINE Start
7
6
5
4
3
2
1
0
Bits 4:0FPLINE Start Position (in pixels) = ( bits4:0 + 2 ) * 8

REG[08h] Horizontal Non-Display Period Register
n/a
n/a
n/a
Horz Non-Disp Period
7
6
5
4
3
2
1
0
Bits 4:0Horizontal Non-Display Period (in pixels) = ( bits4:0 + 4 ) * 8

REG[09h] FPFRAME Start Position Register
n/a
n/a
FPFRAME Start
7
6
5
4
3
2
1
0
Bits 5:0FPFRAME Start Position (in lines)

REG[0Ah] Vertical Non-Display Period Register
Vert Non-Disp Status
n/a
Vert Non-Disp Period
7
6
5
4
3
2
1
0
Bit 7Vertical Non-Display Status = bit7 where { 0=Disabled | 1=Enabled }
Bits 5:0Vertical Non-Display Period (in lines)

REG[0Bh] MOD Rate Register
n/a
n/a
MOD Rate
7
6
5
4
3
2
1
0
Bits 5:0MOD Rate

REG[0Ch] Screen 1 Start Address Register (LSB)
Scrn 1 Start (LSB)
7
6
5
4
3
2
1
0
Bits 7:0Screen 1 Start Address (LSB)

REG[0Dh] Screen 1 Start Address Register (MSB)
Scrn 1 Start (MSB)
7
6
5
4
3
2
1
0
Bits 7:0Screen 1 Start Address (MSB)

REG[0Eh] Screen 2 Start Address Register (LSB)
Scrn 2 Start (LSB)
7
6
5
4
3
2
1
0
Bits 7:0Screen 2 Start Address (LSB)

REG[0Fh] Screen 2 Start Address Register (MSB)
Scrn 2 Start (MSB)
7
6
5
4
3
2
1
0
Bits 7:0Screen 2 Start Address (MSB)

REG[10h] Screen Start Address Overflow Register
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Scrn 1 Start (Bit16)
7
6
5
4
3
2
1
0
Bit 0Screen 1 Start Address (MSB 16)

REG[11h] Memory Address Offset Register
Mem Addr Offset
7
6
5
4
3
2
1
0
Bits 7:0Memory Address Offset

REG[12h] Screen 1 Vertical Size Register (LSB)
Scrn 1 Vert (LSB)
7
6
5
4
3
2
1
0
Bits 7:0Screen 1 Virtual Size (LSB)

REG[13h] Screen 1 Vertical Size Register (MSB)
n/a
n/a
n/a
n/a
n/a
n/a
Scrn 1 Vert (MSB)
7
6
5
4
3
2
1
0
Bits 1:0Screen 1 Virtual Size (MSB)

REG[15h] Look-Up Table Address Register
LUT Addr
7
6
5
4
3
2
1
0
Bits 7:0Look-Up Table (LUT) Address

REG[17h] Look-Up Table Data Register
LUT Data
n/a
n/a
n/a
n/a
7
6
5
4
3
2
1
0
Bits 7:4Look-Up Table (LUT) Data

REG[18h] GPIO Configuration Control Register
n/a
n/a
n/a
GPIO Config
7
6
5
4
3
2
1
0
Bits 4:0GPIO[4:0] Pin IO Configuration

REG[19h] GPIO Status/Control Register
n/a
n/a
n/a
GPIO Status
7
6
5
4
3
2
1
0
Bits 4:0GPIO[4:0] Status

REG[1Ah] Scratch Pad Register
Scratch Pad
7
6
5
4
3
2
1
0
Bits 7:0Scratch Pad

REG[1Bh] SwivelView Mode Register
SwivelView Enable
SwivelView Select
n/a
n/a
n/a
[RSVD]
SwivelView PCLK
7
6
5
4
3
2
1
0
Bit 7SwivelView Mode Enable = bit7 where { 0=Disabled | 1=Enabled }
Bit 6SwivelView Mode Select = bit6 where { 0=Disabled | 1=Enabled }
Bit 2[RESERVED] Must be set to 0.
Bits 1:0SwivelView Mode Pixel Clock Select Bits

REG[1Ch] Line Byte Count Register
Line Byte Count
7
6
5
4
3
2
1
0
Bits 7:0Line Byte Count

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